1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor memory device that operates in synchronism with a clock supplied from the outside of the device.
Conventionally, semiconductor memory devices such as DRAM devices were researched and developed in such a way as to increase the integration density. Recently, CPUs and microprocessors have been advanced to operate at high speeds and it has thus been required to improve the data transfer rate. As semiconductor memory devices which meet the above requirement, various types of semiconductor memory devices have been proposed and placed in practice. Examples of such memory devices are an SDRAM (Synchronous Dynamic Random Access Memory), an FCRAM (Fast Cycle RAM), and a DDR-SDRAM (Double Data Rate SDRAM). Of these types of devices, the DDR-SDRAM utilizes both the rising and falling edges of the clock, so that the data transfer rate can be doubled. Also, the DDR-SDRAM uses a data strobe signal, which ensures a sufficient margin to settle data.
2. Description of the Related Art
FIG. 1 is a block diagram of a system including a controller 100 such as a CPU, and a DDR-SDRAM 200 (hereinafter simply referred to as a memory). FIG. 2 is a timing chart of an operation of the system.
The controller 100 and the memory 200 operate in response to clocks CLK and /CLK of a differential or complementary fashion generated by a clock generator (not shown). Data DQ is transferred between the controller 100 and the memory 200 along with a data strobe signal DQS. The memory 200 is equipped with a terminal DQS used to receive and send the data strobe signal DQS. The controller 100 outputs a command CMD to the memory 200, which is thus instructed to perform a data read (output) operation or a data write (input) operation. An address signal which is output to the memory 200 by the controller 100 is omitted for the sake of simplicity.
A description will be given, with reference to FIG. 2, of the data read and write operations of the system. The controller 100 sends a read command RDAa to the memory 200, which then acquires the command RDAa in synchronism with a rising edge of the clock CLK (timing of xe2x80x9c0xe2x80x9d shown in FIG. 2). The memory 200 switches the data strobe signal DQS from a low level L to a high level H at a timing of xe2x80x9c2xe2x80x9d, which lags behind the receipt of the read command RDAa by two cycles.
The controller 100 and the memory 200 commonly use the data strobe signal DQS with regard to the data input and output operations. Thus, it is necessary for the data strobe signal DQS to be at the low level L for a period that is one cycle earlier than the cycle in which data is read from the memory 200. Such a period is called a preamble period. When data read from the memory 200 is output to a data bus, the memory 200 changes the data strobe signal DQS from the low level L to the high level H. Thus, read data Qa1 is output from the memory 200 to the data bus in synchronism with the rising edge of the data strobe signal DQS.
After the memory 200 switches the data strobe signal DQS to the high level H, the memory 200 alternately changes the data strobe signal DQS to the high level H and the low level L. In synchronism with each of the rising and falling edges of the data strobe signal DQS, pieces of data Qa1, Qa2, Qa1 and Qa2 are serially output to the data bus.
After the pieces of data are output to the data bus, the memory 200 sets a signal line over which the data strobe signal DQS is transferred to a high-impedance state Hi-Z. Thus, it is possible to prevent the data strobe signal DQS output by the memory 200 from interfering with the data strobe signal DQS output by the controller 100. The controller 100 generates an internal signal having edges which are delayed, by a given time, from the rising and falling edges of the data strobe signal DQS, and acquires the read data on the data bus.
Then, the controller 100 outputs a write command WRAb to the memory 200, and sends pieces of write data Db1, Db2, Db1 and Db2 to the memory 200. The controller 10 sets the data strobe signal DQS to the low level L so that the preamble period is defined. Then, the controller 100 alternately switches the data strobe signal DQS to the high level H and the low level L. The memory 200 acquires the pieces of write data in synchronism with the rising and falling edges of the data strobe signal DQS. Then, the controller 100 sets the data strobe signal DQS to the low level L.
In FIG. 2, xe2x80x9cCL=2xe2x80x9d denotes that the column latency is equal to 2, and xe2x80x9cWL=1xe2x80x9d denotes that the write latency is equal to 1. The system shown in FIG. 2 commonly uses the data bus with regard to the data input and output operations. Alternatively, the data input and output operations can be performed through respective, different data buses.
However, the semiconductor memory device 200 has the following disadvantages.
First, it is necessary to define the preamble period because the data strobe signal DQS is used in common to the data read (output) and write (input) operations. the controller 100 and the memory 200 are inhibited from outputting data to the data bus for the preamble period. The preamble period is an empty period, which prevents improvement in the data transfer rate.
Second, it is required that the line carrying the data strobe signal DQS output by the memory 200 is set to the high-impedance state Hi-Z after the data read operation is completed. Thus, the memory 200 must be equipped with a control circuit that sets the data strobe signal line to the high-impedance state.
Third, the data strobe signal DQS is a single-phase signal, and may have high-level and low-level periods which are not equal to each other. This results in different periods for settling or defining data. FIG. 3 shows this problem. The data strobe signal DQS shown in FIG. 3 has a low-level period longer than a high-level period. The data strobe signal DQS is compared with a reference voltage (threshold voltage) Vref, so that the high level H and the low level L are discriminated. In FIG. 3, xe2x80x9ctQSPxe2x80x9d denotes the pulse width of the data strobe signal DQS, and xe2x80x9ctQSQxe2x80x9d denotes a data access time from the data strobe signal DQS. Also, xe2x80x9ctDVxe2x80x9d is a data settlement (definition) width, and xe2x80x9ctACCxe2x80x9d denotes a data access time from the clock CLK. Further, xe2x80x9ctHZxe2x80x9d denotes the period for which the high-impedance state Hi-Z is maintained, and xe2x80x9ctCKQSxe2x80x9d denotes an access time from the clock CLK to the data strobe signal DQS. The situation in which the low-level period of the data strobe signal DQS shown in FIG. 3 is longer than the high-level period thereof results in different data settlement widths tDV.
It is a general object of the present invention to provide a semiconductor integrated circuit device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor integrated circuit device having a newly proposed data transfer method.
The above objects of the present invention are achieved by a semiconductor integrated circuit device operating in synchronism with a clock supplied from the outside of the device, the device including: a first circuit generating, from the clock, an output strobe signal for outputting data from the device and outputting the output strobe signal to the outside of the device.
The above objects of the present invention are also achieved by a semiconductor memory device including: a memory part; a clock receiving part receiving complementary clocks supplied from the outside of the device; and a first circuit generating, from the complementary clocks, complementary output strobe signals for outputting data stored in the memory part and outputting the output strobe signal to the outside of the device.
It is yet another object of the present invention to provide a system include a controller and a memory device. More particularly, the system including: a controller outputting complementary clocks; and a memory device coupled with the controller. The memory device includes: a memory part; a clock receiving part receiving the complementary clocks; and a first circuit generating, from the complementary clocks, complementary output strobe signals for outputting data stored in the memory part and outputting the output strobe signal to the controller.